Reductions in the size and inherent features of semiconductor devices, for example, metal-oxide semiconductor (MOS) devices, have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the MOS device and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the MOS device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the MOS device, which, assuming other parameters are maintained relatively constant, may allow for an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.
To further enhance the performance of MOS devices, stresses may be introduced in the channel region of a MOS device to improve its carrier mobility, which in turn causes the improvement in saturation current, and hence the speed. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction (channel-length direction) and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in the channel-length direction. On the other hand, PMOS and NMOS devices both benefit from tensile stresses in the channel-width direction.
Stresses may be applied to MOS devices in various ways, for example, through stressed etch stop layers and/or stressed shallow trench isolation (STI) regions. FIG. 1 illustrates a layout of a portion of a standard cell, which includes PMOS device 2 and NMOS device 4. PMOS device 2 includes active region 6 and gate electrode 10 over active region 6. NMOS device 4 includes active region 8 and gate electrode 10 over active region 8. The channel regions of PMOS device 2 and NMOS device 4 include portions of active regions 6 and 8 underlying gate electrode 10, respectively.
Assuming there is another active region 12 spaced apart from active region 6 by STI region 14, wherein the spacing between active region 12 and active region 6 is S1, STI region 14 typically applies a compressive stress to active region 6, and hence adversely affects the drive current of PMOS device 2. Further, the magnitude of the stress applied by STI region 14 is affected by the value of spacing S1, and the greater S1 is, the greater the stress will be. On a semiconductor chip formed using standard cell design, there are typically many standard cells placed relatively randomly, and hence the spacing S1 for one standard cell may be significantly different from the spacing S1 for another standard cell. This causes significant variation of the drive currents of the MOS devices. Further, some of the spacings S1 for some of the MOS devices may be so great that the drive currents of the respective MOS devices are affected to a degree not acceptable to certain design. New standard cells are thus needed to solve the above-discussed problems.